nx2: stand in for title 4's tensor-core upscaler and its blit constants
- When a compute program is rejected for tensor-core math, blit its input image (handle at cbuf0+0x90) to its output (cbuf0+0xa0) with bilinear filtering. Title 4 renders at 2560x1440 and upscales to 3840x2160 with a DLSS-style network; this keeps the 4K output fed. EDEN_NX2_TENSOR=stub keeps the program with HMMA as D = C (for experiments). - BlitConstantsPass: vertex shaders reading bank 24 (lowered to 17) get the console-provided blit block synthesized from the render area (texel size, size, UV scale 1, rectangle 0..W-1,H-1). - Debug: EDEN_NX2_CB24_TRACE, upscaler resource description and render target sampling at the fallback. The scene behind the intro dialogue is still black: the tonemap output that feeds the upscaler has no colour although earlier targets do.
This commit is contained in:
Takoroka
parent
26abba68f5
commit
7e5b415e08
7 changed files with 242 additions and 2 deletions
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@ -891,12 +891,20 @@ inline LoweredProgram LowerToMaxwell(std::span<const Instruction> code) {
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// g / g+8 at columns 2i, 2i+1. Rebuilt from shuffles with HFMA2, accumulating in R252/R253.
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// The expansion is correct but large: title 4's 372-HMMA network takes the host driver
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// minutes to compile, so it stays opt-in (the QMD still completes when rejected).
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static const bool enabled = std::getenv("EDEN_NX2_TENSOR") != nullptr;
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if (!enabled) return fail(index, "native matrix multiply (set EDEN_NX2_TENSOR to emulate)");
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// EDEN_NX2_TENSOR=stub keeps the rest of the program but makes every HMMA D = C.
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static const char* const mode = std::getenv("EDEN_NX2_TENSOR");
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if (!mode) return fail(index, "native matrix multiply (set EDEN_NX2_TENSOR to emulate)");
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const u32 a = insn.Bits(24, 8), b = insn.Bits(32, 8), c = insn.Bits(64, 8);
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if ((insn.words[1] & ~0xffU) || (insn.words[2] & ~0xffU) != 0x800 || dest + 2 > 246 ||
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a + 4 > 246 || b + 2 > 246 || (c != 255 && c + 2 > 246))
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return fail(index, "native matrix multiply mode");
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if (std::string_view{mode} == "stub") {
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for (u32 row = 0; row < 2; ++row) {
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if (c == 255) mov_imm(static_cast<u32>(dest) + row, 0);
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else if (c != dest) emit(0x5c98000000000000ULL | predicate | (dest + row) | (u64{15} << 39) | (u64{c + row} << 20));
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}
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break;
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}
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const auto shuffle = [&](u32 target, u32 source_reg) {
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emit(0xef10000000000000ULL | predicate | target | (u64{source_reg} << 8) | (u64{246} << 20) |
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(u64{1} << 29) | (u64{31} << 34) | (u64{7} << 48));
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@ -391,6 +391,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
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Optimization::ConstantPropagationPass(env, program);
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Optimization::PositionPass(env, program);
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Optimization::BlitConstantsPass(env, program);
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Optimization::GlobalMemoryToStorageBufferPass(program, normalized_host_info);
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Optimization::GeometryCompactionPass(program, normalized_host_info);
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@ -28,6 +28,7 @@ void LowerInt64ToInt32(IR::Program& program);
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void RescalingPass(IR::Program& program);
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void SsaRewritePass(IR::Program& program);
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void PositionPass(Environment& env, IR::Program& program);
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void BlitConstantsPass(Environment& env, IR::Program& program);
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void TexturePass(Environment& env, IR::Program& program, const HostTranslateInfo& host_info);
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void LayerPass(IR::Program& program, const HostTranslateInfo& host_info);
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void VendorWorkaroundPass(IR::Program& program);
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@ -74,4 +74,67 @@ void PositionPass(Environment& env, IR::Program& program) {
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}
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}
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}
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// Switch 2 fullscreen blit vertex shaders read a parameter block from constant bank 24 (lowered to
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// bank 17, which games never bind) that the console provides itself. For a blit covering the whole
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// render target it holds: texel size (0x0/0x4, again at 0x10/0x14), size (0x8/0xc), a UV scale of
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// 1 (0x18/0x1c) and the integer source rectangle 0,0..W-1,H-1 (0x50-0x5c).
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void BlitConstantsPass(Environment& env, IR::Program& program) {
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if (env.ShaderStage() != Stage::VertexB) {
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return;
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}
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bool used{};
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for (IR::Block* const block : program.post_order_blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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const IR::Opcode opcode{inst.GetOpcode()};
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if (opcode != IR::Opcode::GetCbufU32 && opcode != IR::Opcode::GetCbufF32 &&
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opcode != IR::Opcode::GetCbufU32x2) {
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continue;
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}
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if (!inst.Arg(0).IsImmediate() || inst.Arg(0).U32() != 17 || !inst.Arg(1).IsImmediate()) {
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continue;
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}
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IR::IREmitter ir{*block, IR::Block::InstructionList::s_iterator_to(inst)};
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const IR::F32 width{ir.RenderAreaWidth()};
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const IR::F32 height{ir.RenderAreaHeight()};
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const auto word = [&](u32 offset) -> IR::U32 {
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switch (offset) {
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case 0x0:
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case 0x10:
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return ir.BitCast<IR::U32>(IR::F32{ir.FPRecip(width)});
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case 0x4:
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case 0x14:
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return ir.BitCast<IR::U32>(IR::F32{ir.FPRecip(height)});
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case 0x8:
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return ir.BitCast<IR::U32>(width);
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case 0xc:
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return ir.BitCast<IR::U32>(height);
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case 0x18:
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case 0x1c:
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return ir.Imm32(0x3f800000U);
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case 0x58:
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return IR::U32{ir.ConvertFToU(32, ir.FPAdd(width, ir.Imm32(-1.0f)))};
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case 0x5c:
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return IR::U32{ir.ConvertFToU(32, ir.FPAdd(height, ir.Imm32(-1.0f)))};
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default:
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return ir.Imm32(0U);
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}
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};
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const u32 offset{inst.Arg(1).U32()};
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IR::Value value;
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if (opcode == IR::Opcode::GetCbufU32x2) {
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value = ir.CompositeConstruct(word(offset), word(offset + 4));
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} else if (opcode == IR::Opcode::GetCbufF32) {
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value = ir.BitCast<IR::F32>(word(offset));
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} else {
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value = word(offset);
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}
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inst.ReplaceUsesWith(value);
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used = true;
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}
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}
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if (used) {
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program.info.uses_render_area = true;
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}
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}
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} // namespace Shader::Optimization
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@ -8,10 +8,12 @@
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#include <bitset>
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#include <cstdlib>
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#include <fstream>
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#include <optional>
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#include "common/assert.h"
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#include "common/logging.h"
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#include "shader_recompiler/exception.h"
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#include "core/core.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/memory_manager.h"
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@ -396,11 +398,145 @@ bool KeplerCompute::DispatchNativeCompute(const NativeQmdScheduler::Descriptor&
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rasterizer->DispatchCompute();
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} catch (const Shader::Exception& error) {
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LOG_ERROR(HW_GPU, "Native compute shader rejected: {}", error.what());
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if (std::string_view{error.what()}.find("matrix multiply") != std::string_view::npos) {
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DescribeNativeResources(qmd);
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// The console runs this on tensor cores; stand in with a plain upscale of its input.
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return UpscaleInsteadOfNativeProgram();
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}
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return false;
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}
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return true;
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}
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// Logs the images a rejected program's handles (constant bank 0, bytes 0x80-0x11c) point to, so a
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// substitute (e.g. an upscale blit for a tensor-core pass) can find its inputs and output.
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void KeplerCompute::DescribeNativeResources(const NativeQmdScheduler::Descriptor& qmd) {
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static u32 described{};
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if (described++ >= 2) return;
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const auto& cbuf = launch_description.const_buffer_config[0];
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const GPUVAddr cbuf_address = (GPUVAddr{cbuf.address_high} << 32) | cbuf.address_low;
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LOG_INFO(HW_GPU, "Native resources: cbuf0 {:#x} size {:#x}, grid {}x{}x{}, block {}x{}x{}, tic pool {:#x}",
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cbuf_address, cbuf.size.Value(), qmd[12], qmd[13] & 0xffff, qmd[14] & 0xffff,
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launch_description.block_dim_x.Value(), launch_description.block_dim_y.Value(),
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launch_description.block_dim_z.Value(), regs.tic.Address());
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for (u32 offset = 0x80; offset < 0x120; offset += 4) {
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const u32 handle = memory_manager.Read<u32>(cbuf_address + offset);
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const u32 tic_index = handle & 0xfffff;
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if (handle == 0 || tic_index > regs.tic.limit) continue;
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const auto tic = GetTICEntry(tic_index);
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LOG_INFO(HW_GPU, " handle @{:#x} = {:#x}: tic {} address {:#x} {}x{} format {:#x} types {}/{}/{}/{}",
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offset, handle, tic_index, tic.Address(), tic.Width(), tic.Height(),
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static_cast<u32>(tic.format.Value()), static_cast<u32>(tic.r_type.Value()),
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static_cast<u32>(tic.g_type.Value()), static_cast<u32>(tic.b_type.Value()),
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static_cast<u32>(tic.a_type.Value()));
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}
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}
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// Title 4's upscaler reads the tonemapped frame through the texture handle at cbuf0+0x90 and
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// writes the output resolution image through the surface handle at cbuf0+0xa0 (from its
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// TLD/SUST operands). Blit one to the other with bilinear filtering when both are plain 2D images
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// of the same format and the output is larger.
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bool KeplerCompute::UpscaleInsteadOfNativeProgram() {
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const auto& cbuf = launch_description.const_buffer_config[0];
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const GPUVAddr cbuf_address = (GPUVAddr{cbuf.address_high} << 32) | cbuf.address_low;
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const auto image = [&](u32 offset) -> std::optional<Texture::TICEntry> {
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const u32 tic_index = memory_manager.Read<u32>(cbuf_address + offset) & 0xfffff;
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if (tic_index > regs.tic.limit) return std::nullopt;
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return GetTICEntry(tic_index);
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};
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const auto input = image(0x90), output = image(0xa0);
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if (!input || !output || input->format != output->format || input->Address() == 0 ||
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output->Address() == 0 || output->Width() <= input->Width() || !input->IsBlockLinear() ||
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!output->IsBlockLinear())
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return false;
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using RTFormat = Tegra::RenderTargetFormat;
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RTFormat format{};
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switch (input->format) {
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case Texture::TextureFormat::A2B10G10R10: format = RTFormat::A2B10G10R10_UNORM; break;
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case Texture::TextureFormat::A8B8G8R8: format = RTFormat::A8B8G8R8_UNORM; break;
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case Texture::TextureFormat::B10G11R11: format = RTFormat::B10G11R11_FLOAT; break;
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case Texture::TextureFormat::R16G16B16A16: format = RTFormat::R16G16B16A16_FLOAT; break;
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default: return false;
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}
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const auto surface = [&](const Texture::TICEntry& tic) {
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Fermi2D::Surface result{};
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result.format = format;
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result.linear = Fermi2D::MemoryLayout::BlockLinear;
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result.block_width.Assign(tic.block_width);
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result.block_height.Assign(tic.block_height);
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result.block_depth.Assign(tic.block_depth);
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result.depth = 1;
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result.width = tic.Width();
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result.height = tic.Height();
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result.addr_upper = static_cast<u32>(tic.Address() >> 32);
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result.addr_lower = static_cast<u32>(tic.Address());
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return result;
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};
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const Fermi2D::Config config{
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.operation = Fermi2D::Operation::SrcCopy,
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.filter = Fermi2D::Filter::Bilinear,
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.must_accelerate = true,
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.dst_x0 = 0,
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.dst_y0 = 0,
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.dst_x1 = static_cast<s32>(output->Width()),
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.dst_y1 = static_cast<s32>(output->Height()),
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.src_x0 = 0,
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.src_y0 = 0,
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.src_x1 = static_cast<s32>(input->Width()),
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.src_y1 = static_cast<s32>(input->Height()),
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};
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// Debug: does the input hold anything? Download it once and count non-zero words.
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if (static u32 sampled{}; sampled++ == 20) {
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const auto sample = [&](const Texture::TICEntry& tic) {
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const u64 size = u64{tic.Width()} * tic.Height() * 4;
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if (const auto device = memory_manager.GpuToCpuAddress(tic.Address())) {
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rasterizer->FlushRegion(*device, size, VideoCommon::CacheType::All);
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}
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u32 nonzero{}, samples{};
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u64 sum{};
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for (u64 offset = 0; offset < size; offset += 4096 + 4) {
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const u32 word = memory_manager.Read<u32>(tic.Address() + offset);
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++samples;
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nonzero += word != 0;
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sum += (word & 0x3ff) + ((word >> 10) & 0x3ff) + ((word >> 20) & 0x3ff);
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}
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LOG_INFO(HW_GPU, "Upscale fallback image {:#x}: {}/{} sampled words non-zero, mean channel {}",
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tic.Address(), nonzero, samples, samples ? sum / (samples * 3) : 0);
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};
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sample(*input);
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sample(*output);
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// Every 2560x1440 target the in-game passes draw to (from EDEN_NX2_RT_TRACE).
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for (const GPUVAddr address : {0x8116a03000ULL, 0x8117ae5000ULL, 0x8114b62000ULL,
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0x8115a63000ULL, 0x8117904000ULL, 0x8114a02000ULL}) {
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Texture::TICEntry fake = *input;
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const u64 size = 2560ULL * 1440 * 4;
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if (const auto device = memory_manager.GpuToCpuAddress(address)) {
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rasterizer->FlushRegion(*device, size, VideoCommon::CacheType::All);
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}
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u32 nonzero{}, samples{}, distinct{};
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u32 last{};
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for (u64 offset = 0; offset < size; offset += 4096 + 4) {
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const u32 word = memory_manager.Read<u32>(address + offset);
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++samples;
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nonzero += word != 0;
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distinct += word != last;
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last = word;
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}
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LOG_INFO(HW_GPU, "Upscale fallback target {:#x}: {}/{} non-zero, {} changes", address, nonzero,
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samples, distinct);
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(void)fake;
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}
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}
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const bool done = rasterizer->AccelerateSurfaceCopy(surface(*input), surface(*output), config);
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static u32 logged{};
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if (logged++ < 4) {
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LOG_INFO(HW_GPU, "Upscale fallback {:#x} {}x{} -> {:#x} {}x{}: {}", input->Address(),
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input->Width(), input->Height(), output->Address(), output->Width(),
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output->Height(), done ? "blitted" : "not accelerated");
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}
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return done;
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}
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void KeplerCompute::ProcessLaunch() {
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
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@ -234,6 +234,8 @@ public:
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private:
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bool DispatchNativeCompute(const NativeQmdScheduler::Descriptor& descriptor);
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void ProcessNativeReportSemaphore(u32 argument);
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void DescribeNativeResources(const NativeQmdScheduler::Descriptor& qmd);
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bool UpscaleInsteadOfNativeProgram();
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bool ProcessNativeMethod(Core::System& system, u32 method, u32 argument, bool is_last_call);
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NativeQmdScheduler native_qmd;
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bool native_mode{};
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@ -399,6 +399,35 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
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TraceWindowTarget(*maxwell3d, *gpu_memory, is_indexed ? "draw-indexed" : "draw",
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is_indexed ? maxwell3d->draw_manager.draw_state.index_buffer.count
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: maxwell3d->draw_manager.draw_state.vertex_buffer.count);
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// EDEN_NX2_CB24_TRACE: for draws whose vertex shader reads bank 24, show the inline
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// constant buffer upload target (CB_ADDRESS) and its first words.
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if (static const bool trace = std::getenv("EDEN_NX2_CB24_TRACE") != nullptr; trace) {
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const auto& regs = maxwell3d->regs;
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const u64 vs = (u64{regs.pipelines[1].reserved[0] & 0xff} << 32) | regs.pipelines[1].reserved[1];
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static u32 logged{};
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if ((vs == 0x11471c9a00 || vs == 0x11471ca600 || vs == 0x11471cd300) && logged++ < 3) {
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std::array<u32, 24> words{};
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gpu_memory->ReadBlockUnsafe(regs.const_buffer.Address(), words.data(), sizeof(words));
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LOG_INFO(HW_GPU, "bank24 draw vs={:#x}: CB_ADDRESS {:#x} size {:#x} offset {:#x}: {:08x}", vs,
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regs.const_buffer.Address(), regs.const_buffer.size, regs.const_buffer.offset,
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fmt::join(words, " "));
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// Search every bound vertex-stage buffer for render-target-size values.
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const auto& stage = maxwell3d->state.shader_stages[0];
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for (u32 slot = 0; slot < Tegra::Engines::Maxwell3D::Regs::MaxConstBuffers; ++slot) {
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const auto& buffer = stage.const_buffers[slot];
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if (!buffer.enabled || buffer.size == 0) continue;
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std::vector<u32> data(std::min<u32>(buffer.size, 0x10000) / 4);
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gpu_memory->ReadBlockUnsafe(buffer.address, data.data(), data.size() * 4);
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for (size_t i = 0; i < data.size(); ++i) {
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const u32 w = data[i];
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if (w == 0x45200000 || w == 0x44b40000 || w == 0x39cccccd || w == 0x3a360b61 ||
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w == 0x44a00000 || w == 0x44340000 || w == 2559 || w == 1439) {
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LOG_INFO(HW_GPU, " slot {} +{:#x} = {:#x}", slot, i * 4, w);
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}
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}
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}
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}
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}
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// EDEN_NX2_RT_TRACE: log the first draw to every distinct colour target (debug aid).
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if (static const bool trace = std::getenv("EDEN_NX2_RT_TRACE") != nullptr; trace) {
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static std::set<std::tuple<GPUVAddr, u32, u32, u64, u64>> seen;
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